In many electronic systems it is necessary to determine the magnitude of the vector sum of orthogonal signals. For example, in digital TV receivers it is convenient to perform automatic flesh color correction by manipulating the magnitude and phase of the chrominance vector. This vector, however, is present in the form of quadrature signals represented by the I and Q or (R-Y) and (B-Y) color mixture signals. Thus, to perform the required manipulation, the magnitude of the chrominance vector must be determined from its component parts.
It is well known that the magnitude of a vector may be ascertained by generating the square root of the sum of the squares of the amplitude values of its orthogonal components. This may be accomplished with the use of multiplier circuits for squaring the amplitude values, adder circuitry for summing the squares, and square root circuitry for determining the square root of the sum. Alternatively, the function may be performed by producing the logarithms of the component amplitude values, appropriately combining the logarithms and generating the antilogs to produce the magnitude values of the vector. A further approach is to combine the magnitude value of the component vectors as an address code applied to a memory programmed to produce output values corresponding to the magnitude of the vector sum of the applied address codes.
It will be readily appreciated by those skilled in the art of signal processing that each of the foregoing methods require significant amounts of processing hardware and increases superlinearly with increasing signal bits. In addition, the necessary components are not readily available to perform real time processing for wide band signals. These factors are particularly restrictive shortcommings in a digital TV receiver context where it is desirable to maintain circuit components to a minimum and the components are to be realized in VLSI integrated form.